1. Technical Field
The present invention relates generally to semiconductor package structures having liquid coolers integrally packaged with first level chip modules and, more specifically, apparatus and methods for integrally packaging a liquid cooler device with in a first level chip package structure wherein the liquid cooler device is thermally coupled directly to the back side of an integrated circuit chip flip-chip mounted on flexible chip carrier substrate, and wherein the liquid cooler device is mechanically coupled to the package substrate through a metallic stiffener structure that is bonded to the flexible package substrate to provide mechanical rigidity to the flexible package substrate.
2. Discussion of Related Art
Technological innovations in semiconductor fabrication and packaging technologies have enabled development of high performance, and high integration density semiconductor chip modules. As chip geometries are scaled down and operating speeds are increased and chip packages become more compact, however, power densities are increased resulting in more heat generation per unit area. The increased power density poses practical limitations to the level of integration density and performance that may be achieved. Indeed, the ability to implement chip modules with higher densities and higher performance is limited primarily by the ability to effectively cool the chip modules during normal operation. For instance, as heat is generated by IC chips during normal operation, cooling structures must be employed to provide sufficiently low thermal resistance paths between the chips and ambient air or a circulating liquid coolant to adequately remove heat and maintain the operating temperature of the chips low enough to assure continued reliable operation. In high performance, high density chip package structures, air cooling solutions are not capable of removing heat due to very high power density or due to space and/or air flow limitations, thereby requiring liquid cooling solutions (e.g., water coolant).
Moreover, effective cooling solutions are important in high performance, high density package structures to minimize mechanical stresses that may occur over temperature cycling (caused by power cycling) due to the differences in thermal expansion between different components of the chip package structure. More specifically, package components formed from materials having different coefficients of thermal expansion (CTE) tend to expand and contract by different amounts during thermal cycling, which is a phenomenon known as “CTE mismatch”. The CTE represents the ratio of change in dimensions to original dimensions per degree rise in temperature, expressed in ppm/° C. CTE mismatch denotes the difference in the coefficients of thermal expansions of two materials or components joined together, which produces strains and stresses at joining interfaces or in attachment surfaces.
By way of example, in conventional packaging technologies, chip level packages can be constructed with one or more chips mounted on a thin flexible first level package substrate, such as an organic laminate build up package substrate, using micro solder bump connections, referred to as C4's (controlled collapse chip connection). A key issue with first level organic package substrates is the CTE mismatch between silicon chips (˜3 ppm/C) and the composite laminate carrier substrate (15-20 ppm/C) to which the chips are attached via C4s. Such CTE mismatch can result in mechanical stresses on the C4 connections between the chip and the organic carrier substrate during thermal cycling. As these mechanical stresses are applied over repeated thermal cycles, the C4 connections may become fatigued and fail. To counteract stress to C4 connections, underfill materials may be applied between the chip and carrier to protect the C4 solder bumps.
Moreover, even when underfill material is used to maintain the structural integrity of C4 contacts, the stress generated by the CTE mismatch between the silicon chip and organic substrate, for example, can result in bowing or bending of substrates and chips. For instance, the differences in thermal expansion between the silicon chip and the organic carrier substrate can cause the chip to warp by 60 microns or more after processing, and cause the substrate to be even more substantially warped. Such bending/bowing can not only generate significant stresses and strains in the electrical contacts between the chip and substrate, but the chip may be subjected to a high tensile stress, so a small defect or scratch can result in chip cracking or delamination of the organic substrate layers. This warpage resulting from CTE mismatch between silicon chip and organic carrier substrate during thermal cycling becomes worse as the chip size increases and this is particularly problematic for lidless packages where the backside surface of the chip is exposed.
To counteract possible warping of package, various types of mechanical stiffening structures may be employed to provide mechanical rigidity to flexible package substrates such as polymer substrates and organic laminate build up package substrates. For instance, conventional packaging techniques utilize mechanical stiffener structures, e.g., planar stiffener plates, package lid structures, and a combination of stiffener plates and package lid structures, which are bonded to package substrates in ways that counteract mechanical stresses arising from differential thermal expansion between chip and substrate, for example, to reduce flexure during thermal cycling and otherwise improve the overall structural reliability of the package. Various conventional semiconductor chip package structures in which mechanical stiffening structures are used with first level SCM (single chip module) chip packages to reduce flexure, will be now be discussed in detail below with reference to FIGS. 1A/B, 2A/B and 3.
FIGS. 1A and 1B schematically illustrate an embodiment of an electronic module (10) having a conventional framework for packaging a single chip module (SCM) with a liquid cooling module onto a circuit board (20). In particular, FIG. 1A is a schematic side view of an electronic module (10) comprising a circuit board (20) (PCB, node card, printed wiring board, printed circuit card, etc.), a 1st level chip package (30) and cooler device (40) in a stacked configuration. The chip package (30) generally comprises an organic laminate package substrate (31) (or “chip carrier”), an IC (integrated circuit) chip (32), and a package lid (33). The cooler (40) is mechanically attached to the circuit board (20) using an attachment device (50). FIG. 1B is a schematic top plan view of the electronic module (10) along line 1B-1B in FIG. 1A, excluding the package lid (33), cooler device (40) and attachment devices (50).
As depicted in FIGS. 1A and 1B, the semiconductor IC chip (32) is flip-chip mounted to a top-side surface of the chip carrier substrate (31) using an array of fine pitch solder balls (34) such as C4 (Controlled Collapsed Chip Connect) solder balls that provide electrical connections between an array of I/O pads on the active surface of the chip (32) and a footprint of corresponding I/O pads on the top-side surface of the chip carrier substrate (31). The IC chip (32) is mechanically coupled to the organic chip carrier substrate (31) using an underfill material (35) disposed between the IC chip (32) and the organic chip carrier (31) encapsulating the C4 connections (34). The chip (32) is disposed in a central region of the substrate (31) and surrounded by underfill material (35) which extends beyond the edge of the chip (32) to form a fillet. The underfill material (35) (e.g., epoxy) is a rigid material that serves to redistribute mechanical stresses in the interface between the chip (32) and the carrier substrate (31) caused by the CTE mismatch between the chip carrier (31) and the chip (32), to thereby minimize stress applied to the C4 connections (34). Other devices such as decoupling capacitors (37) are shown mounted on the first surface of the chip carrier (31) using micro solder balls. In FIG. 1B, the decoupling capacitors (37) are shown to be placed along two opposite sides of the chip (32).
The chip carrier substrate (31) may comprise electrical contacts formed on the first surface thereof to provide electrical interconnections between the chip (32) and devices (37) using wiring inside the substrate (31) (not shown). As depicted in FIG. 1A, an array of larger pitch solder balls (36) provide electrical connections between an array of contact pads formed on a second major (bottom) surface of the substrate (31) and a corresponding array of I/O contacts formed on the top surface of the circuit board (20), providing an area array connection known as a ball grid array (BGA). The circuit board (20) includes a plurality of wiring layers (21) that are connected to one or more plated through holes (22). The plated through holes (22) provide electrical connections between the array of I/O contacts on the top surface of the board (20) with the wiring layers (21) connected to the plated through holes (22).
In the exemplary framework of FIGS. 1A-B, the package lid (33) functions as a mechanical stiffener member and a heat spreader. The package lid (33) includes an outer rim (33a) that surrounds and defines a lid cavity (33b) region that encloses the integrated circuit chip (32) and other devices (37) when the package lid (33) is mounted to the chip carrier (31). The package lid (33) is attached to the chip carrier (31) by bonding the lid outer rim (33a) to the outer peripheral surface region of the chip carrier (31) using a layer of adhesive material (38). In this regard, the package lid (33) serves as a stiffener member that provides supports for the chip carrier substrate (31) to counteract thermal/mechanical stresses and reduce semiconductor package warpage and improve the overall reliability. The package lid (33) can be made of copper with a thickness of 0.5 mm to 2.0 mm. The package lid (33) design can vary depending on the application but the package lid (33) design is an important consideration in the overall package framework as a package lid which is too thick and too stiff can result in excessive stress and failure in the package.
The package lid (33) also serves as a heat spreader for cooling the IC chip (32) wherein the package lid (33) extends over the back surface of the chip (32) wherein the inner surface of the lid cavity (33b) is thermally coupled to the backside of the chip (32) using a layer of thermal interface material (TIM) (39). The TIM layer (39) is typically formed of a mechanically compliant, thermally conductive material which provides mechanical compliance and serves as a primary thermal path to transfer heat from the IC chip (32) to the package lid (33). The package lid (33) is thermally coupled to the cooling device (40) using a second layer of TIM (45). The TIM layer (39), package lid (33) and second TIM layer (45) provide a thermal path for conducting heat from the backside of the chip (32) to the cooling device (40) where the heat is dissipated by the cooling device (40) via air or liquid cooling. In the conventional framework of FIG. 1A, the second TIM layer (45) would typically consist of a filled paste or grease, or a phase change material such as a filled wax, which are reworkable, as opposed to a filled adhesive or gel material which require curing at 100-150 C and are not easily reworkable. For most TIMs, the filler material has a high thermal conductivity such as silver, graphite, or ceramic particles, for example. The first TIM layer (39) between the chip (32) and the bottom surface of the package lid (33) would typically be a filled adhesive or gel material as opposed to a fluid material such as pastes or greases that could be “pumped out” by the package displacements during thermal cycling. This would be less of a concern for the second TIM layer (45) when, for instance, the cooler (40) and package lid (33) are formed of the same material, e.g., copper, or materials having similar CTEs.
The cooling device (40) may be an air cooled heat sink or a liquid cooler device having a plurality of thermal fins (41) that define open channels (42) through which air or liquid may flow to remove heat from the thermal fins (41). The cooler (40) is mechanically attached to the mother board (20) using the attachment device (50) which is configured to apply a compressive load to hold the cooler (40) against the top surface of the package lid (33). As depicted in FIG. 1B, a plurality of mounting holes (51) are formed through the mother board (20) in proximity to each corner of the carrier substrate (31) for insertably receiving the attachment devices (50). This attachment scheme uses hardware that requires holes (51) to be formed in the electrical board (20) which blocks some wiring channels of the circuit board (20). In this conventional framework, the SCM chip package (30) would be attached to the circuit board (20) by a solder reflow process if BGA or CGA electrical interconnects are used, or plugged into a socket if PGA electrical interconnects are used, or aligned to an LGA connector if LGA electrical interconnects are used. The second TIM layer (45) would then be dispensed onto the lid (33), or the bottom of the cooler device (40), and they would be joined and the cooler device (40) secured to the circuit board (20) by the attachment devices (50). As described above, it would be desirable to use a TIM2 (45) material which is reworkable and does not require curing at an elevated temperature.
FIGS. 2A and 2B schematically illustrate another embodiment of an electronic module having a conventional framework for packaging a single chip module (SCM) with a cooling module onto a circuit board (20). In particular, FIG. 2A is a schematic side view of an electronic module (11) including a printed circuit board (PCB) (20) (or node card, printed wiring board, or printed circuit card), a 1st level chip package (60) and cooler device (40) in a stacked configuration with the chip package (60) interposed between the circuit board (20) and the cooler device (40). FIG. 2B is a schematic top plan view of the electronic module (11) along line 2B-2B in FIG. 2A excluding the planar package lid (64), cooler device (40) and attachment devices (50). Except for the first level chip package (60), the electronic module (11) illustrated in FIGS. 2A-B has a conventional framework that is similar to that of the electronic module (10) in FIGS. 1A-1B, and therefore, a detailed explanation is not required.
The chip level package (60) includes a separate stiffener member (62) and a planar package lid (64). As shown in FIG. 2A, the stiffener member (62) is attached to a perimeter region of the organic laminate chip carrier (31) with a layer of adhesive material (61) and the planar package lid (64) is attached to the stiffener member (62) with a layer of adhesive material (63). As depicted in FIG. 2B, the stiffener member (62) has a rectangular frame-like structure with an outer border (62a) and inner border (62b). The outer border (62a) has a rectangular shape that corresponds to the outer perimeter of the chip carrier substrate and the inner border (62b) has a rectangular shape that defines an inner open region which aligns to the inner surface region of the carrier substrate (31) in the area occupied by the chips (32) and surrounding devices (37).
As compared to the conventional package structure (10) of FIGS. 1A/1B, the conventional package structure (11) of FIGS. 2A and 2B can be constructed in a process by which the stiffener member (62) is attached to the organic carrier (31) prior to the chip mounting process, which reduces possible warping of the substrate (31) and maintains the flatness of the substrate (31) before the chip (32) is attached to the chip carrier substrate (31), and further provides the requisite mechanical support during a solder reflow process when the chip (32) is mounted to the chip carrier (31). The types of adhesive used to form layers (61) and (63) will vary depending on the desired mechanical properties.
In this conventional framework, the SCM chip package (60) would be attached to the circuit board (20) by a solder reflow process if BGA or CGA electrical interconnects are used, or plugged into a socket if PGA electrical interconnects are used, or aligned to an LGA connector if LGA electrical interconnects are used. A second TIM layer (45) would than be dispensed onto the lid (33), or the bottom of the cooler device (40), and they would be joined and the cooler device (40) secured to the circuit board (20) by the attachment devices (50). As described above, it would be desirable to use a TIM2 (45) material which is reworkable and does not require curing at an elevated temperature.
FIG. 3 schematically illustrates another embodiment of an electronic module having a conventional framework for packaging a single chip module (SCM) with a cooling module onto a circuit board (20). In particular, FIG. 3 is a schematic side view of an electronic module (12) including a printed circuit board (PCB) (20) (or node card, printed wiring board, or printed circuit card), a 1st level chip package (70) and cooler device (40) in a stacked configuration with the chip package (70) interposed between the circuit board (20) and the cooler device (40). The cooler (40) is mechanically attached to the circuit board (20) using an attachment device (50). Except for the first level chip package (70), the electronic module (12) illustrated in FIG. 3 has a conventional framework with similar components of the electronic modules (10) and (11) discussed above, and therefore, a detailed explanation is not required.
With the electronic module (12) of FIG. 3, the chip level package (70) includes a rectangular shaped stiffener member (72) that is attached to a perimeter region of the organic laminate chip carrier (31) with a layer of adhesive material (71), but the chip level package (70) does not include a package lid structure (as compared to the chip package (30) with package lid (33) and the chip package (60) with package lid (64)). The electronic module (12) is a lidless SCM structure in which the stiffener member (72) may have a structure similar to the stiffener member (62) depicted in FIG. 2B, but the thickness of the stiffener member (72) can be varied to obtain a given stiffness. In the conventional embodiment of FIG. 3, a heat spreading function is achieved by thermally bonding the backside of the chip (32) directly to the bottom surface of the cooler device (40) using a mechanically compliant, thermal interface layer (TIM) (73).
The conventional package structure (12) of FIG. 3 provides a lower thermal resistance thermal path between the backside of the chip (32) and cooler (40), as compared to the conventional lidded SCM package structures (10) and (11) in which lid structures are disposed in the thermal path between the chip (32) and cooling device (40). Indeed, a lower thermal resistance path is achieved by eliminating the thermal resistance of a package lid between the chip (32) and cooler (40) and the thermal resistance that exists due to the TIM2 layer (45) between the package lid and cooler (40). Indeed, in FIG. 3, the thermal resistance in the path between the chip (32) and cooler (40) is based on the thickness and material used to form the TIM layer (73). Although a lidless chip package structure (12) of FIG. 3 can theoretically provide increased thermal performance, the ability to actually achieve a low thermal resistance TIM layer (73) between the chip (32) and cooler (40) in the framework of FIG. 3 is problematic by virtue of the increased mechanical complexity of having the cooler (40) attached to the circuit board (20) and the chip (32) attached to the laminate carrier (31) which is attached to the board (20).
More specifically, in the framework of FIG. 3, the cooler (40) is mechanically attached to the circuit board (20) using the attachment device (50), which would typically apply a compressive load to hold the cooler (40) in a fixed position against the backside surface of the chip (32) With this framework, it is important to obtain and maintain the requisite bond line (i.e., desired uniform thickness of TIM (73) between the chip (32) and cooler (40). Thus, when the cooler (40) is being mounted, it is important to ensure that the cooler (40) is maintained flat against the back surface of the chip (32), and that excessive force is not applied to the chip (32), and that the chip (32) is protected against excessive forces from shock or vibration so as to obtain and maintain the requisite bond line of TIM layer (73). The TIM layer (73) would typically consist of a filled paste or grease, as it is undesirable to use a filled adhesive or gel materials which would require curing at 100-150° C. and which are not easily reworkable. However, the disadvantage of using a paste or grease is its tendency to pump out from the space between the backside of the chip (32) and the cooler (40) as a result of thermal excursions where chip warpages vary due to the mechanical complexity of having the cooler (40) attached to the board (20) and the chip (32) attached to the laminate carrier (31) which is attached to the board (20).
In this conventional framework, the SCM chip package (70) would be attached to the circuit board (20) by a solder reflow process if BGA or CGA electrical interconnects are used, or plugged into a socket if PGA electrical interconnects are used, or aligned to an LGA connector if LGA electrical interconnects are used. A TIM layer (73) would then be dispensed onto the back side of the chip (32), or the bottom of the cooler device (40), and they would be joined and the cooler device (40) secured to the circuit board (20) by the attachment devices (50). As described above, it would be desirable to use a TIM (73) material which is reworkable and does not require curing at an elevated temperature.
State of the art chip packaging technologies typically utilize metallic material such as copper to construct chip package cooler devices (e.g., liquid coolers) or heat sink structures because copper has a very high thermal conductivity, and can be readily machined/etched/formed into fine features and dimensions (e.g., micro channel cooler devices) with low manufacturing costs. Typically, copper liquid cooler devices are used for cooling chips mounted on ceramic multichip modules (MCMs). However, in each of the conventional frameworks discussed above, the cooler (40) is physically attached to the circuit board (20), the footprint of the cooler (40) must be larger than the footprint of the chip (32) and extend past the outer periphery of the chip (32) so as to connect to the board (20). This large size metallic cooler posed practical limitations such as follows:
When a BGA (ball grid array) or CGA (column grid array) attachment techniques are used to mechanically/electrically connect the carrier (31) to the circuit board (20), a large size metallic cooler (40) results in a large thermal mass that is not compatible with the BGA or CGA reflow process. Moreover, the resulting weight of the SCM module may be too high preventing the module from self-aligning to the printed circuit board pads and can compress the liquid solder excessively thereby causing shorts during the solder reflow process. Therefore, with a BGA or CGA electrical interconnect to the circuit board (20) a large size metallic cooler may need to be attached to the SCM chip package after the reflow process used to attach the SCM chip package to the circuit board. For other mechanical area array connection methods such as LGA (land grid array) or a pin grid array (PGA), where a compressive force must be applied for actuation, such compressive forces may result in a thin and/or non uniform thickness of the TIM layer between the liquid cooler and chip.
In this regard, when designing chip packages, various factors must be considered, such as carrier structure, types of package materials and underfill used, the fabrication process flow, chip size, thermal properties, etc., to minimize or prevent package defect mechanisms and structural failures as a result of strains and stresses that may arise from thermal cycling during production, joining processing, and use.